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ANSim: A Fast and Versatile Asynchronous Network-On-Chip Simulator
Tom Glint, Jitesh Sah, , Joycee Mekie
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 2020-October
Pages: 619 - 622
In a large chip, an asynchronous Network-on-Chip (NoC) is a suitable candidate for establishing an interconnection network between varied components. Architectural level simulation is an accepted methodology for evaluating such systems. In this paper, we propose a fast and versatile Asynchronous Network-on-Chip (NoC) Simulator - ANSim, which brings down the simulation time by 25 x, compared to the state of the art simulators. It can model and analyze all synchronous, asynchronous and mixed synchronous-asynchronous system of cores connected through NoC. ANSim can model routers with different delays, routers with asynchronous arbitration, connected in a wide range of topologies. ANSim supports individual routers modeled to have varying timing constraints. Further, it supports synthetic and real-workloads and produces system-level latency, throughput, power, power-gating and arbitration reports. ANSim has been verified against RTL models of NoCs and other RTL verified simulators. An open-source synchronous NoC router, TNoC and its asynchronous derivative are used to demonstrate ANSim's usefulness and features.
About the journal
JournalData powered by TypesetProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
Open AccessNo